Generally, resistance random access memory devices (ReRAMs), a type of nonvolatile memory utilize principles that electrical resistance characteristics are varied depending on an applied voltage. The ReRAMs are memory devices that make use of On/Off state of current according to the resistance variable characteristics due to the magnitude of the applied voltage. These ReRAMs have various advantages of relatively speedy access time, low power consumption, and reduction in process fault due to a simple memory cell structure.
As illustrated in FIG. 1A, an example of the ReRAMs is disclosed in U.S. Patent Application Publication No. 2006/0250837, entitled “NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL”, proposed by Herner et al.
Referring to FIG. 1A, a diode 16 and a resistance-switching element 18 are stacked between a bottom conductor 12 and a top conductor 14, thereby forming one memory layer 20. This memory layer 20 is stacked in plural, resulting in forming a highly dense monolithic three dimensional memory array. FIG. 1B schematically illustrates a resistance random access memory device 10 having the above-described monolithic three dimensional memory array.
With reference to FIG. 1B, when the resistance random access memory device 10 is embodied by forming a three dimensional memory array 30, the number of process steps required for stacking N memory layers may be equal to the value “N×S” that multiplies the number S of process steps required for defining a plurality of memory cell blocks by forming one memory layer 20 by the number N of stacked memory layers. That is, as the number of stacked layers increases, the number of process steps linearly increases.
The bottom conductor 12 and the top conductor 14 extend in an orthogonal direction, and a memory cell is formed at a cross-point therebetween. In general, the bottom conductor 12 may form word-lines, while the top conductor 14 may form bit-lines. For instance, when the number of word-lines 12 is K and the number of bit-lines 14 is M, the number of memory cell blocks, which is formed on one memory layer 20, may be K×M. In this case, when the number of stacked memory layers 20 is N, the number of memory cell blocks to be formed may be N×K×M.
The number of decoders required for accessing K×M memory cell blocks on one memory layer 20 may be the value “K+M” that is the sum of the number K of word-lines 12 and the number M of bit-lines 14. If N memory layers 20 are stacked, the number of decoders may be the value “(N×K)+(N×M)” that is the sum of the number “N×K” of stacked word-lines 12 and the number “N×M” of stacked bit-lines 14. That is, as the number of stacked layers increases, the number of decoders linearly increases. Accordingly, an area and the number of process steps are required for forming the decoders.